Journal Publications/Letters (reverse chronological order)

    • Jinal Tapar, Saurabh Kisen, Kumar Prashant, Kaushik Nayak, and Naresh Kumar Emani, "Enhancing the optical gain in GaAs nanocylinders for nanophotonic applications," in Journal of Applied Physics (Vol.127, Issue 15), April 2020.

    • S. Venkateswarlu, and K. Nayak, "Ambient Temperature Induced Device Self-heating Effects on Multi-Fin Si CMOS Logic Circuit Performance in N-14 to N-7 scaled Technologies", in IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1530-1536, April 2020.

    • Akhil. S, S. Venkateswarlu, and K. Nayak, "Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10 nm node SOI n-FinFET", IEEE Transactions on Electron Devices , vol. 66, no. 11, November 2019.

    • S. Venkateswarlu, Akhil. S, S. G. Singh and K. Nayak, "Ambient Temperature Induced Device Self-heating Effects on Multi-Fin Si n-FinFET Performance", IEEE Transactions on Electron Devices , vol. 65, no. 7, July 2018.

    • M. Bajaj, K. Nayak, S. Gundapaneni and V. Ramgopal Rao, "Effect of metal gate granularity induced random fluctuations on Si gate-all-around nanowire MOSFET 6-T SRAM cell stability", IEEE Transactions on Nanotechnology , vol. 15, no. 2, Mar. 2016.

    • K. Nayak, S. Agarwal, M. Bajaj, K. V. R. M. Murali, and V. Ramgopal Rao, “Random dopant fluctuation induced variability in undoped channel Si gate all around nanowire n-MOSFET,” IEEE Transactions on Electron Devices , vol. 62, no. 2, pp. 685 - 688, Feb. 2015.

    • A. Konar, J. Mathew, K. Nayak, M. Bajaj, R. Pandey, S. Dhara, K. V. R. M. Murali and M. Deshmukh, "Carrier transport in high mobility InAs nanowire junctionless transistors," ACS Nano Letters , Feb. 2015.

    • K. Nayak, S. Agarwal, M. Bajaj, P. J. Oldiges, K. V. R. M. Murali, and V. Ramgopal Rao, "Metal gate granularity induced threshold voltage variability and mismatch in Si gate-all-around nanowire n-MOSFETs," IEEE Transactions on Electron Devices , vol. 61, no. 11, pp. 3892 – 3895, Nov. 2014.

    • K. Nayak, M. Bajaj, A. Konar, P. J. Oldiges, K. Natori, H. Iwai, K. V. R. M. Murali, and V. Ramgopal Rao, "CMOS logic device and circuit performance of Si gate all around nanowire MOSFET," IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3066 – 3074, Sep. 2014.

    • K. Nayak, M. Bajaj, A. Konar, P. J. Oldiges, H. Iwai, K. V. R. M. Murali, and V. Ramgopal Rao, "Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits", Jpn. J. Appl. Phys.,, vol. 53, no. 4S, pp. 04EC16-1-04EC16-7, 2014.

    • B. Bhushan, K. Nayak, and V. Ramgopal Rao, "DC compact model for SOI tunnel Field-Effect Transistors ", IEEE Transactions on Electron Devices,, vol. 59, no. 10, pp. 2635 - 2642, Oct. 2012.

 

      Conference Papers (reverse chronological order)

    • Y. Pullaiah, Naresh Kumar Emani,and K. Nayak, "Device Electrostatics and High Temperature Operation of Oxygen Terminated Boron Doped Diamond MOS Capacitor and MOSFET”, 4th IEEE Electron Devices Technology and Manufacturing (EDTM) conference 2020 , Penang, Malaysia, Mar 16-18, 2020.

    • Akhil S., S. Venkateswarlu, and K. Nayak, "Superior Work Function Variability Performance of Horizontally Stacked Nanosheet FETs for Sub-7-nm Technology and Beyond”, 4th IEEE Electron Devices Technology and Manufacturing (EDTM) conference 2020 , Penang, Malaysia, Mar 16-18, 2020.

    • S. Venkateswarlu, Akhil S., and K. Nayak, "Impact of Phonon Boundary Scattering on Self-heating Effects in Stacked Si Nano-sheet FET in sub-7nm Logic Technologies”, XXth International Workshop on Physics of Semiconductor Devices: IWPSD, Kolkata, India , Dec 17-20, 2019.

    • S. Venkateswarlu, Akhil S., and K. Nayak, "Improved Electro-Thermal Performance in FinFETs using SOD Technology for 7nm node High Performance Logic Devices", International Conference on Solid State Devices and Materials (SSDM), , Nagoya University, Japan, Sep. 2 - 5, 2019.

    • Jinal Tapar, Saurabh Kisen, K. Nayak, and Naresh Emani, "Optimizing the Gain in Semiconductor Nanostructures for All-dielectric Active Metamaterial Applications", International Conference on Materials for Advanced Technologies (ICMAT), , Marina Bay Sands, Singapore, 23-28 June 2019.

    • K. Nayak, M. Bajaj, A. Konar, P. J. Oldiges, H. Iwai, K. V. R. M. Murali, and V. Ramgopal Rao, "Negative differential conductivity in gate all-around Si nanowire FETs and its impact on circuit performance", Extended Abstracts of International Conference on Solid State Devices and Materials (SSDM), , pp. 90-91, Fukuoka, Japan, Sep. 24-27, 2013.

    • M. A. Khaderbad, K. Nayak, M. Yedukondalu, M. Ravikanth, S. Mukherji, and V.Ramgopal Rao, “Metallated Porphyrin self assembled monolayers as Cu diffusion barriers for the nano-scale CMOS technologies”, Proceedings of the 8th IEEE International Conference on Nanotechnology (IEEE NANO 2008), , pp. 167-170, Arlington, Texas USA, August 18-21, 2008.

    • K. Nayak, P. Kulkarni, Deepu A., V. Sitaraman, S. Punidha, A. Saha, M. Ravikanth, S. Mitra, S. Mukherji, & V. Ramgopal Rao, “Patterned microfluidic channels using self-assembled Hydroxy-phenyl Porphyrin monolayer”, Proceedings of the 7th IEEE International Conference on Nanotechnology (IEEE NANO 2007), , pp. 1235-1239, Hong Kong, August 2-5, 2007.