Sparsh Mittal

Assistant Professor

Department of Computer Science and Engineering

Indian Institute of Technology, Hyderabad, India.

Email: sparsh0mittal at gmail dot com; sparsh at iith.ac.in

Profiles at Google Scholar, Academia.edu, ResearchGate and LinkedIn

I am no longer accepting any interns, so do not send any mail for this.

Research Interests

Overall area: Computer architecture (CPUs and GPUs), VLSI, high-performance computing, approximate computing, processor architectures for AI

Specific research interests: architectural simulation, energy-efficient and reliable main memory and cache design, low-power computing.

Memory technologies: SRAM, non-volatile memory (NVM) devices (STT-RAM, PCM, ReRAM), DRAM memory and eDRAM cache

Awards and Honors

1.    My research has been covered by several technical news websites, e.g. Phys.org, InsideHPC 1, InsideHPC 2, InsideHPC 3, InsideHPC 4, Primeur Magazine, StorageSearch, Data-Compression.info, TechEnablement, ScientificComputing, SemiEngineering (semiconductor engineering), ReRAM forum and HPCWire.

2.     Received Distinguished Contribution rating at ORNL based on 2013-2014 performance appraisal. This rating recognizes the top 10 percent of staff. 

3.     Received Outstanding Contribution rating at ORNL based on 2014-2015 performance appraisal. Also received a performance award of $1000.

4.     Gave an invited presentation at Memory for HPC Systems session at ISC, Germany 2016. ISC is a top conference with 3000 attendees and bi-annual Top500 list is announced here.

5.     Best student paper candidate in SC 2014

6.    ECpE fellowship from Electrical and Computer Engineering Department, Iowa State University, USA of $2500 in 2008.

7.    Peer Research Award from Iowa State University, USA of $200 in 2013.

8.    Topper in Electronics batch of year 2008 in ECE department at IIT Roorkee and received Institute Silver Medal for this.

9.    Institute Silver Medal for Best B.Tech project award in Electronics and Computer Engineering (ECE) Department at IIT Roorkee.

10.                  Sumer Chand Jain Scholarship of INR 10,000 from IIT Roorkee.

11.  Best Student Award from High School (named MHS, Jaipur, Rajasthan, India) in 2004.

 

Selected Publications

Designing SOT-RAM based GPU register file: ISVLSI 2017

Addressing read-disturbance issue in STT-RAM cache: CAL 2017 (1)

Addressing write-disturbance issue in PCM memory: CAL 2017 (2)

Improving soft-error reliability of GPU register file: VLSID 2017

Inductive charge pump for 3D stacked PCM: GLSVLSI 2017

Write overhead management in NVM caches and main memory: HPDC 2016, IEEE TVLSI 2016, IEEE CAL 2015, IEEE MASCOTS 2015, GLSVLSI 2014, ISVLSI 2014, USENIX INFLOW 2014

Power management in SRAM and eDRAM caches: HPDC 2014, IEEE TVLSI 2013, ICCD 2013, VLSID 2013

Improving soft-error reliability of SRAM caches: GLSVLSI 2016

Application resiliency modeling and metric: SC 2014

Survey papers:

System-level

On CPU-GPU heterogeneous computing

On big.LITTLE-style asymmetric multicore processors (for example, Samsung's Exynos 5 Octa) (summary PPT)

On comparison between energy efficiency of GPUs, FPGAs and CPUs

System component-level: architectural techniques for

GPU register file (summary PPT) and GPU caches

CPU register file

TLBs (translation lookaside buffer) (summary PPT)

Value prediction and value locality

Architectural Management Techniques For

Approximate computing and storage (summary PPT)

Cache partitioning in multicore processors (summary PPT)

Power management of GPUs, data centers, embedded systems, SRAM caches, DRAM main memory and PCM main memory

Near-threshold computing (summary PPT)

Data compression in cache and main memory (summary PPT)

Soft-error resilience for CPUs and GPUs (summary PPT)

Managing process variation in CPUs and GPUs (summary PPT)

Addressing soft-error issues in non-volatile memories (summary PPT)

Cache prefetching in CPUs

Cache bypassing in CPUs, GPUs and CPU-GPU systems and SRAM, NVM and stacked-DRAM caches (summary PPT)

Cache locking

On memory technologies:

Stacked-DRAM caches (summary PPT), eDRAM and NVM caches, domain wall memory (racetrack memory) (summary PPT), NVMs (e.g. Flash) for storage systems and main memory

On question answering systems (natural language processing)

 

See http://publicationslist.org/sparsh0mittal for full publication list and download links.

The PowerPoint slides of a few conference presentations are available here. Summaries of survey papers can be obtained by clicking on summary PPT.

Funded Proposals

2017/04: SERB early career research (ECR) award, title: Secure and Reliable Non-volatile Memories for Ultra-low Power Applications

Open-source software released

1.    DESTINY: DESTINY is an acronym for 3D design-space exploration tool for SRAM, eDRAM and non-volatile memory. It is a tool for modeling both 2D and 3D caches designed with five prominent memory technologies: SRAM, eDRAM, PCM, STT-RAM and ReRAM, which covers both conventional and emerging technologies. In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. Here are manual, DATE 2015 paper and extended technical report. Source-code is available from ORNL and github repos (pick any repo, they are mirror repos). See its news coverage on ReRAM forum. Join DESTINY mailing list or see archive of previous conversations.

The proverb goes, write your own destiny. Hence, we have written our own [tool named] DESTINY. J

2.    Both serial and parallel versions of code of red-black SOR (successive over-relaxation) method in three state-of-the-art languages, viz. Chapel (from Cray Inc.), D (also called dlang, from Digital Mars) and Go (also called golang, from Google) can be downloaded for academic use from this link. They were used in this paper. Chapel version of the code has been incorporated in Chapel performance test suite/examples.

 

Professional Background

Postdoctoral research associate at Oak Ridge National Lab, USA (2013-2016)

PhD from Iowa State University (ISU), Ames, Iowa, USA (2008-2013).

BTech from Indian Institute of Technology (IIT) Roorkee, Uttarakhand, India (2004-2008).

Professional Activity

Reviewer for:

ACM: Computing Surveys (3 times), TACO (2 times), TECS (2 times)

IEEE: CAL (3 times), Intelligent Systems, ISVLSI, JETCAS, Trans. on Computers (TC), Trans. On VLSI Systems, TCAD (2 times), DFT, HiPC student research symposium

Springer: Cluster Computing, J. of Supercomputing, Springer book High Performance Computing in Power and Energy Systems

IET CDT, MDPI Sustainability, Concurrency and Computation (2 times)

Teaching

2017 Spring: CS5360 Advanced computer architecture and CS3523 Operating system (with S. Peri)

2016 Fall: CS2323 Computer Architecture (with A. Franklin) and CS5410 Advanced memory system architecture

Student Mentoring

Graduate students:

Rujia Wang, University of Pittsburgh, USA 2016/05-2016/07

Seonglyong Gong, University of Texas, Austin, USA, 2016/05-2016/08

Matthew (Matt) Poremba, Penn State University, USA, 2014/06-2014/09

Undergraduate students:

Sai Susmita (NIT, Trichy), Madhuri Gupta (NIT, Sikkim), Alina Bhutia (NIT, Sikkim), Suparno Ghoshal (Heritage Inst of Tech.)

Invited Presentations/Seminars

* VelTech University, Chennai, India 2017

* PARCOMPTECH, Bangalore, India 2017 (organized by CDAC and DeitY)

* ISC Conference, Germany, 2016/06 (link)

* University of Michigan, 2015/11

* New York University 2016/02

Technical Skills

Programming Languages/tools: C, C++, CUDA, Go (from Google), X10 (from IBM), Matlab, Simulink, System Generator (Xilinx), python, LaTeX, Gnuplot.

Architectural Simulators: Simplescalar, GEMS, Gem5, Sniper, MARSS, GPGPUSim.

Office Address

E-621, IIT Hyderabad, Kandi,

Hyderabad, India, 502258